The open architecture quietly rewiring the chip business
RISC-V is the open instruction set architecture the whole industry has started building on, and RISC-V IoT is where the shift lands first. This is the hub: what RISC-V is, why it matters for connected and edge hardware, and where the rest of the series digs in.
The short version
Every processor speaks an instruction set. For decades you had two that mattered, and both belonged to someone: x86 to Intel and AMD, Arm to Arm. You paid to play, you built to their roadmap, and you hoped they did not change their mind. RISC-V is the awkward third option nobody could licence away, because there is nothing to licence. It is an open, royalty-free standard anyone can implement.
That sounds like a footnote for chip nerds. It is not. Over 10 billion RISC-V cores had shipped by 2025, and the analysts at Omdia reckon the architecture reaches roughly a quarter of the processor market by 2030. This is not a thought experiment any more. It is already inside things you own.
RISC-V could do to processor architecture what Linux did to operating systems. IoT is simply where that shift shows up first, because the edge is filling with devices that need to think locally, not just phone home.
What RISC-V actually is
It started as a three-month summer project at UC Berkeley in 2010. The “V” is a Roman five: the fifth RISC design out of Berkeley after RISC-I, RISC-II, SOAR and SPUR. The team wanted a clean instruction set for teaching and research, put no patents on the specification, and accidentally handed the industry the open ISA it had been waiting on.
The stewardship sits with RISC-V International, founded as the RISC-V Foundation in 2015 and reincorporated in Switzerland in 2020 to keep it out of any single country’s reach. The full history, the ownership question and the “is it really open source” argument each get their own post. If you want the basics first, start with What Is RISC-V?, then Who Owns RISC-V? and Is RISC-V Really Open Source?
Why IoT feels it first
The neat way to picture RISC-V is as a contract sitting in the middle of the stack. Software is written to the contract above. Silicon implements the contract below. Because the contract is open, dozens of vendors can build to it and still run the same software, and you are no longer married to whoever owns the ISA.
IoT sits right where that openness pays off. Margins are thin, volumes are huge, and a licence fee per core is the difference between a viable product and a spreadsheet that never closes. Add the pull toward local intelligence and you get hardware that has to sense, decide and only then talk. RISC-V does the compute; the connectivity layer does the talking. That is where the low-power cellular link matters, whether you frame it as RedCap for the intelligent edge or its 5G RedCap companion. For the full argument, see Why RISC-V Matters for IoT.
The Arm question
Everyone wants to know whether RISC-V kills Arm. Wrong question. The interesting difference is the model, not the winner. Here is the shape of it.
| Licensed model (Arm, x86) | RISC-V | |
|---|---|---|
| The ISA itself | Owned and licensed by one firm | Open standard, royalty-free |
| Getting a core | Licence the IP or buy the chip | Buy it, licence it, or design your own |
| Customising the ISA | Limited, on the owner’s terms | Add your own extensions |
| Supplier choice | Tied to the licensor | Many vendors, one software target |
| If the vendor pivots | You are exposed | The standard stays open |
In practice the two coexist inside the same chip more often than they fight. We take the comparison apart in RISC-V vs Arm: What’s the Difference? and answer the blunt version in Can RISC-V Replace Arm?
From microcontroller to edge brain
RISC-V scales. At the bottom it is a tiny microcontroller core buried in a sensor node, the kind of part Espressif shipped when the ESP32-C3 became its first fully RISC-V chip. At the top it runs full Linux on an application processor in a gateway. The thing that stops that range turning into chaos is a common target, and in 2024 the community ratified one: the RVA23 profile, a baseline set of features that operating systems and compilers can rely on across vendors. It is also the baseline for the Android RISC-V ABI.
Between those poles is most of IoT: the microcontrollers themselves, the RTOS layer, embedded Linux, and the gateways stitching it together. Each gets its own spoke, from RISC-V Microcontrollers Explained through RISC-V and Embedded Linux to What Is RVA23?. The reason it all matters now is the same reason edge AI is having a moment: the vector maths that machine learning leans on is exactly what RISC-V’s Vector Extension was built for. Start with RISC-V and Edge AI and RISC-V and TinyML.
Security, and who gets to control the silicon
An open ISA has a quietly useful property: you can inspect it. For anyone who cares about what their hardware is actually doing, an auditable instruction set beats a black box. That thread runs through on-device security, secure elements and identity, and it is why RISC-V keeps turning up in RISC-V Security Explained.
It also explains the politics. Europe is pouring money into RISC-V through the European Processor Initiative and the newer DARE project precisely because an open standard cannot be export-controlled out from under you. China is leaning on it as a sovereignty hedge for the same reason. Neither story is really about chips; both are about not depending on someone else’s roadmap. We cover them in RISC-V and European Semiconductor Sovereignty and RISC-V and China’s Semiconductor Strategy.
Where this goes
The likeliest future for RISC-V is not a headline. It is invisibility: billions of cores doing unglamorous work inside devices nobody thinks about, the way Linux ended up under most of the internet without anyone noticing. If that happens, IoT and the edge are where it happened first. That is the bet this series is built on, and we spell it out in The Future of RISC-V: 2030 and Beyond.
Last updated 6 August 2026. Sources: RISC-V origin and governance per RISC-V International and UC Berkeley records; RVA23 profile ratified October 2024 (RISC-V International); RISC-V Vector Extension v1.0 ratified 2021; cumulative shipments (10 billion-plus cores by 2025) per RISC-V International; 2030 market-share estimate per Omdia.
