What RISC-V is, without the hand-waving
So what is RISC-V? In plain terms, it is an open, royalty-free instruction set that any chipmaker can build on without paying a toll. Here is what that means, why it is put together the way it is, and why it keeps turning up in IoT hardware.
First, what an instruction set even is
Every processor, from the chip in a smart plug to the one in a data centre, only understands a fixed list of very simple commands. Add these two numbers. Fetch this from memory. Jump to there. That list, and the exact rules for how you write those commands, is the instruction set architecture, or ISA. It is the contract between software and silicon: the software promises to only ask for things on the list, and the hardware promises to do them.
Get that idea and the rest of RISC-V falls into place. The ISA is a common language. As long as your software speaks it and your chip speaks it, the two work together, even if they came from completely different companies.
So what makes RISC-V different
Here is the twist. For decades the instruction sets that mattered were owned. x86 belongs to Intel and AMD. Arm belongs to Arm. If you wanted to build a chip using one, you paid for the privilege and you built to the owner’s rules.
RISC-V is the one you do not have to ask permission to use. It came out of the University of California, Berkeley in 2010, the fifth in a line of RISC designs from the same university, which is where the “V” comes from. The team deliberately put no patents on the specification and released it openly. Today it is looked after by RISC-V International, a neutral non-profit that moved to Switzerland in 2020 precisely so that no single government could pull the plug. There is a fuller version of that story in Who Owns RISC-V?, and the wider picture sits in the series hub.
It is built like Lego, on purpose
This is the part that trips up newcomers, so it is worth slowing down. RISC-V is not one fixed design. It is a small mandatory core with a set of optional bolt-ons called extensions. You take the base and add only the bits your product needs.
The base is a plain integer instruction set, written RV32I for 32-bit or RV64I for 64-bit. Everything else is a letter you can choose to include. A tiny sensor chip might use RV32IMC. A Linux-capable processor might use RV64GC. Those letters are not marketing; each one is a defined block of extra instructions.
| Extension | What it adds | Why an IoT designer cares |
|---|---|---|
| I (base) | Core integer instructions | The mandatory minimum; every RISC-V chip has it |
| M | Multiply and divide | Real arithmetic without slow software workarounds |
| A | Atomic operations | Safe behaviour across multiple cores and an RTOS |
| C | Compressed 16-bit instructions | Smaller code, cheaper flash, lower unit cost |
| F / D | Floating-point maths | Sensor data and signal processing |
| V | Vector operations | The muscle behind on-device AI |
The point of all this modularity is efficiency. A traditional owned ISA hands you the whole thing whether you use it or not. RISC-V lets a chip designer keep a low-cost microcontroller lean and pile the heavy extensions onto a beefier part, all while targeting the same base. One family, wildly different products.
What “open” actually buys you
Open does not mean free chips falling from the sky. RISC-V silicon still costs money to design and make. What is free is the instruction set itself, and that changes the economics in three quiet but useful ways: no per-core licence fee, no single supplier you are locked to, and the freedom to add your own custom extensions if your workload is unusual enough to justify it.
The ISA is open; the chips are not necessarily. Anyone can build a RISC-V processor, sell it, or design one from scratch, and it will still run software written for the same base. That is the whole trick.
Whether that openness makes RISC-V “better” than Arm is a genuinely more interesting question than it first looks, and it gets its own post in RISC-V vs Arm: What’s the Difference?. If the open-source label itself is nagging at you, Is RISC-V Really Open Source? picks that apart honestly.
Why a beginner in IoT should care
You could file all this under “interesting for chip people” and move on, except RISC-V has already arrived in the exact hardware this site is about. When Espressif built the ESP32-C3, one of the most common Wi-Fi microcontrollers in hobbyist and commercial IoT, it dropped its old proprietary core and used RISC-V instead. Over 10 billion RISC-V cores had shipped by 2025, and a great many of them are doing unglamorous work inside connected devices.
That is the thread running through this whole series. RISC-V is not an abstract standards-body argument. It is turning up in sensors, gateways and edge boxes, and the low cost and customisability that make it attractive are the same properties IoT has always chased. Now that you know what it is, the natural next questions are who controls it and how it stacks up against the incumbent. Both are one click away below.
Last updated 6 August 2026. Sources: RISC-V origin at UC Berkeley (2010) and governance under RISC-V International (founded 2015, incorporated in Switzerland 2020) per RISC-V International; base ISA and standard extensions per the ratified RISC-V specifications; ESP32-C3 RISC-V core per Espressif; cumulative shipments (10 billion-plus cores by 2025) per RISC-V International.
