The boring standard that makes the whole thing work
RVA23 is not the sort of thing that gets a keynote, but it might be the most important RISC-V milestone of the lot. It is the profile that tells software exactly what a RISC-V application chip is guaranteed to contain, and in doing so it quietly fixes the one problem that could have held the whole architecture back.
The problem hiding inside RISC-V’s best feature
The thing everyone loves about RISC-V is that it is modular. A base instruction set, then a pick-and-mix of optional extensions, so a chip designer includes only what the product needs. Brilliant for the people making silicon. A nightmare, left unchecked, for the people writing software.
Because if every chip can choose its own combination of extensions, then the word “RISC-V” on a datasheet tells a software developer almost nothing. Does this part have the vector instructions my AI library needs? The bit-manipulation ones my crypto code assumes? Maybe. Maybe not. Build your binary assuming a feature the silicon lacks and it does not run slowly, it crashes. That is fragmentation, and it is the exact trap that has swallowed open platforms before.
What a profile actually is
The fix is a profile. Rather than listing extensions one letter at a time, a profile bundles a ratified set of them under a single name that everyone agrees to target. RISC-V International has issued a few now, RVA20 and RVA22 before this one, each a snapshot of “here is the sensible baseline for an application processor this year.”
RVA23, ratified in October 2024, is the current one for 64-bit application-class chips, the parts that run a full Linux or Android. The deal is simple and powerful. If a chip claims RVA23 compliance, software can assume every extension in that profile is present. One binary, built once, runs across every compliant part. No feature-detection gymnastics, no per-chip builds.
This is the whole point: a profile turns RISC-V’s flexibility from a liability back into an asset. Chip designers keep their freedom below the line, and software vendors get a guaranteed floor to build on above it. RVA23 is where those two interests are made to agree.
What changed from RVA22
| Feature | RVA22 | RVA23 | Why it matters |
|---|---|---|---|
| Vector (V) extension | Optional | Mandatory | Accelerates AI/ML, crypto, media at the edge |
| Hypervisor (H) extension | Optional | Mandatory | Virtualization and secure separation |
| Vector crypto | Not available | Optional add-on | Much faster than scalar crypto |
| Control-flow integrity | Not present | Optional (landing pads, shadow stack) | Hardware defence against exploits |
The two that carry the weight are at the top. Making the vector extension mandatory means every RVA23 chip can do serious math-heavy work, which is precisely what edge AI needs. Making the hypervisor mandatory means every RVA23 chip can run virtualized and isolated workloads, which is what servers, and increasingly gateways, want.
Why this matters beyond the spec sheet
Profiles are dry reading, but the consequences are not. RVA23 is the baseline requirement for the Android RISC-V ABI, which means Google has drawn a line and said this is what a RISC-V chip must be to run Android. Ubuntu and Red Hat have made the same move for their RISC-V builds, targeting RVA23 so they compile against one predictable feature set. That is the mechanism behind the RISC-V and embedded Linux story: the distributions could commit properly once there was a stable target to commit to.
It also answers, quietly, one of the oldest knocks against the architecture. When people ask whether RISC-V can replace Arm, part of Arm’s advantage was always that it gave software a consistent, predictable target. Profiles are how RISC-V closes that gap. Not by being cleverer silicon, but by being a dependable platform, which for a mass software ecosystem matters far more.
Where it lands for IoT and the edge
For connected hardware, the mandatory vector extension is the headline. It means every application-class RISC-V chip carrying the RVA23 badge can do the math-heavy work that edge AI and on-device inference demand, without waiting on an optional accelerator that may or may not be fitted. The baseline just got a lot more capable, and a lot more uniform.
That is the platform edge intelligence needs: predictable, capable silicon that software can target with confidence. It is the connective tissue under everything from the gateway to the smart camera, and it is why the profile deserves more attention than its unglamorous name suggests. For how it all fits the wider shift, the RISC-V and IoT cornerstone pulls the threads together.
Last updated 23 August 2026. Sources: RVA23 Profile ratified 21 October 2024 per RISC-V International; Vector and Hypervisor extensions mandatory in RVA23, both optional in RVA22, per the ratified RVA23 profile specification v1.0 and RISC-V International; RVA23 is the baseline requirement for the Android RISC-V ABI per RISC-V International.
