The open architecture is already in your gadgets. Nobody sent a memo.
RISC-V development boards now run from ten-cent microcontrollers to Linux-class single-board computers, and a lot of them are already sitting inside shipping IoT gear. Here is where the open silicon lands, and where it lands first.
You are probably shipping it already
Here is the quiet part. RISC-V did not arrive in IoT with a keynote and a countdown clock. It arrived inside parts you were already buying. The smart plug with the Espressif chip in it. The Matter sensor on the shelf. The blue dev board on your bench that you bought because it was five quid and it was there. Somewhere in that pile is an open instruction set doing the work, and nobody thought to mention it.
That is the honest shape of adoption in this industry. It is not a switch that gets flipped. It is a substitution that happens one bill of materials at a time, inside components chosen for price and radios and footprint, where the core architecture is close to the last thing anyone checks. If you have used an ESP32-C3, an ESP32-C6, or a Raspberry Pi Pico 2, you have run RISC-V whether you clocked it or not. The cornerstone of this series sets out why that matters for connected hardware, and the microcontroller rundown goes a level deeper.
The spectrum runs from ten cents to a Linux desktop
What makes RISC-V interesting for IoT is not any single board. It is the range. At one end sits the WCH CH32V003, a 32-bit part with a QingKe core, 16 KB of flash and a price tag under twenty cents, cheap enough to design in without a meeting about it. At the other end sit quad-core parts running Ubuntu with an NPU bolted on, aimed squarely at the gateway and the edge-AI box. Same instruction set. One open ISA now covers the entire IoT compute ladder, from the disposable sensor node up to the embedded-Linux class.
That continuity is the whole argument. A designer can move up the performance curve without changing ecosystems, toolchains or mental models, which is exactly the lock-in problem the open model was meant to solve. It is also why RISC-V reads as an IoT story before it reads as a datacentre one: IoT is the market that actually needs the full spread, from the cheapest thing that can read a thermistor to the smart camera doing inference on the pole.
A working shortlist
You do not need to memorise the catalogue. You need a feel for which part answers which IoT problem. Here is a representative spread, mapped to the job rather than the spec sheet.
| Part / board | Where it fits in IoT | Tier | Rough price |
|---|---|---|---|
| WCH CH32V003 | Disposable-cheap sensor node, bare-metal, battery or coin-cell | Deep-embedded MCU | chip under $0.20, boards near $1 |
| Espressif ESP32-C3 | Connected sensor or wearable, Wi-Fi plus Bluetooth LE | Connectivity MCU | modules roughly $1 to $3 |
| Espressif ESP32-C6 | Matter, Thread and Zigbee smart-home endpoint | Connectivity MCU | dev boards around $5 |
| Raspberry Pi Pico 2 (RP2350) | Prototyping and a dual-architecture hedge on one board | MCU | $5 |
| StarFive VisionFive 2 / Milk-V Mars (JH7110) | Linux gateway, light server, general edge node | App-class SBC | roughly $70 to $100 |
| Milk-V Duo / BeagleV Ahead / Banana Pi BPI-F3 | On-device inference with an NPU or TPU, smart camera, robotics | Edge-AI SBC | roughly $30 to $150 |
Prices are approximate and drawn from an early-2025 roundup, so treat them as order-of-magnitude rather than gospel. The pattern is what counts: a single ISA answering everything from a doorbell button to a camera that recognises a face.
Connectivity is where it bites first
If you want to know where RISC-V goes mainstream in IoT before anywhere else, follow the radios. The ESP32-C6 pairs a RISC-V core with 2.4 GHz Wi-Fi 6, Bluetooth LE and an 802.15.4 radio, which is the exact combination you need to build Matter endpoints, Thread devices and Zigbee kit. Its sibling the ESP32-H2 does the low-power mesh side without Wi-Fi. Nobody buying these is buying them for the instruction set. They are buying the connectivity, and the connectivity now sits on a RISC-V core as a matter of course.
That is the beachhead. The smart-home and Matter tier is high volume, cost-driven and radio-led, which is precisely the environment where an open, royalty-free core wins on the bill of materials before it wins any argument about architecture. The compute is doing the boring part. The radio sells the chip. And once the endpoint is talking, something still has to carry the traffic back over the wide-area link, which is where a connectivity layer like RedCap earns its keep alongside the edge silicon.
The takeaway: RISC-V is not entering IoT top-down through flagship processors. It is entering bottom-up through the cheapest connected parts, where it is already the default in a good slice of Wi-Fi and Matter silicon.
The Linux end, and the edge-AI question
Climb the ladder and the story changes character. The StarFive JH7110 powers a clutch of sub-$100 single-board computers – VisionFive 2, Milk-V Mars – that boot mainline Linux and behave like a slightly slower Raspberry Pi. Push further and you hit boards with real accelerators: NPUs and TPUs rated in the low single-digit TOPS, aimed at edge AI on smart cameras, robotics and gateways that would rather not send every frame to the cloud.
This is the tier that gets the press, and it is also the tier where RISC-V is still doing the hard yards against a mature Arm ecosystem. It works, but it is early. The interesting part for IoT is operational rather than architectural: once you have a fleet of these gateways in the field, the architecture underneath matters far less than how you manage them, which is where an IoT platform like ThingsBoard does the unglamorous work of provisioning, telemetry and updates. The silicon is a means. The fleet is the product.
Where it actually goes mainstream first
Strip away the desktop-RISC-V daydreams and the near-term picture is clear enough. Late in 2025, RISC-V International, citing analysis from the SHD Group, said the architecture had reached roughly 25 percent market penetration, with forecasts of well over 20 billion chips shipping annually by the start of the next decade. Espressif’s RISC-V parts alone are reckoned to be deployed across tens of billions of connected devices. Whether those headline percentages describe the whole semiconductor market or only the segments RISC-V has entered is worth reading the small print on, but the direction is not in doubt.
Read it through an IoT lens and the answer is unromantic. Mainstream adoption lands first in the invisible, high-volume, cost-sensitive MCU tier – the parts nobody photographs for the launch post – and disproportionately in silicon sourced from vendors with a reason to avoid Western IP licensing. The glamour sockets, the phones and the laptops, come later if they come at all. The doorbell got there first.
Keep it honest: the market-share figures are analyst forecasts, not shipping receipts, and they carry the usual caveats about small base years and generous CAGRs. The trend is real. The exact numbers are a projection.
The reality check
None of this means the ecosystem is finished. At the microcontroller end it is genuinely mature: compilers, debuggers and RTOS support are all there, and for most IoT firmware written in C you would struggle to notice the core underneath. At the Linux and edge-AI end it is patchier, with driver gaps, board-specific quirks and the general sense of a platform still filling in. The fragmentation that used to haunt RISC-V is being answered by profile baselines like RVA23, which give software a common target to build against instead of a spread of one-off configurations.
So the sober version is this. RISC-V is not going to replace Arm in your IoT stack next quarter. It is going to keep quietly turning up inside the parts you already specify, first at the cheap connected end and then, more slowly, up the ladder toward the gateway and the camera. If you design connected hardware, the practical move is not to bet the roadmap on it. It is to stop being surprised when it shows up.
Last updated 6 August 2026. Board line-up and indicative pricing draw on Saad Imtiaz and Jean-Francois Simon, “The RISC-V Architecture: 16 Boards and MCUs You Should Know” (Elektor, February 2025). RISC-V core content of the ESP32-C3, ESP32-C6, ESP32-H2, ESP32-P4 and the Raspberry Pi RP2350 confirmed against Espressif and Raspberry Pi documentation. Market-penetration and shipment figures per RISC-V International and the SHD Group (2025), with earlier forecasts from Omdia; figures are analyst projections and are cited as such.