Two instruction sets, one board decision you have to live with
The RISC-V vs Arm embedded question is not really about which architecture is cleverer. It is about which one you are willing to commit your next board, your firmware and the next five years of support to. Arm is the incumbent everyone knows. RISC-V is the open challenger that keeps turning up in real silicon. Here is how they actually differ where it counts.
The question is commitment, not philosophy
Plenty of ink gets spilled on whether open beats licensed as a matter of principle. If you build embedded systems for a living, that argument is a pub conversation. The real question lands the day you spec a board: do you commit the design to an Arm core, with everything that flows from that, or to RISC-V, with everything that does not yet flow from that. Pick wrong and you are not out a debate, you are out a respin, a toolchain migration, or a product that cannot get the middleware it needs.
So this is the practical version of the comparison. If you want the plain-English difference between the two architectures in general, the RISC-V vs Arm explainer covers that ground. This piece is about the embedded decision specifically.
Where things stand: Arm is still the one to beat
No point pretending otherwise. Arm’s Cortex-M line is the de facto standard for 32-bit microcontrollers, and the numbers back it up. By core architecture, Arm Cortex-M held about 68% of the microcontroller market in 2025, with RISC-V the fastest-growing challenger, forecast to expand at roughly 15% a year to 2031, according to Mordor Intelligence. Every major MCU vendor, STMicroelectronics, NXP, Microchip, Renesas, Silicon Labs, ships Cortex-M parts by the shelf-full.
That incumbency is the thing you are really weighing RISC-V against. It is not just silicon, it is a decade and a half of tooling, training, reference designs, certified stacks and engineers who already know the part. RISC-V does not have to be better than Arm to win a design. It has to be enough better on the axis you care about to justify leaving all that behind.
The differences that actually move the decision
Strip out the noise and the choice comes down to a handful of axes. On licensing and bill of materials, Arm charges a licence plus a per-chip royalty on the core IP, which is baked into the price of every Cortex-M part you buy. RISC-V carries no ISA licence and no royalty, which is exactly why cost-driven vendors gravitated to it first and why it shows up in the cheapest parts on the market.
On ecosystem, Arm wins on maturity and RISC-V wins on momentum. Arm has CMSIS, commercial IDEs, an enormous middleware catalogue and a well-worn certification path. RISC-V leans on the open toolchain, GCC, LLVM and OpenOCD for debug, which is genuinely capable but occasionally rough at the edges. The Raspberry Pi RP2350 is a fair example: its Hazard3 RISC-V cores need a recent GCC, sometimes built from source, where the Arm side just works out of the box.
Then there is the thing RISC-V can do that Arm structurally cannot: let you add your own instructions. If your workload benefits from a custom extension, RISC-V is an open ISA you are allowed to extend. Arm’s is not. For most products that is irrelevant, but for the ones where it matters, it matters a lot.
The lock-in is smaller than it feels. Both Zephyr and FreeRTOS run on Arm and RISC-V, and if your firmware is written against an RTOS and a HAL rather than raw assembly, most of it is ISA-agnostic. The real switching cost sits in the peripherals, the vendor tooling and the certified stacks, not the instruction set underneath.
Side by side, for embedded designers
| Decision factor | Arm (Cortex-M) | RISC-V |
|---|---|---|
| Licensing and royalties | Architecture licence plus per-chip royalty on the core | No ISA licence, no royalty (open standard) |
| Ecosystem maturity | Very mature: CMSIS, commercial IDEs, vast middleware | Growing fast: GCC, LLVM, OpenOCD, occasional friction |
| Silicon choice | Every major MCU vendor, huge catalogue | Expanding: Espressif, WCH, GigaDevice, Raspberry Pi, SiFive, Andes |
| Custom instructions | Not permitted, fixed ISA | Custom extensions allowed |
| Hardware security | TrustZone-M, established PSA certification route | Improving, varies by implementation |
| RTOS support | Zephyr, FreeRTOS and most others | Zephyr, FreeRTOS, the same major RTOSes |
| Market position (2025) | Around 68% of MCU market by core | Challenger, roughly 15% CAGR to 2031 |
The RP2350 shows where this is heading
If you want a single part that captures the state of play, it is the Raspberry Pi RP2350 behind the Pico 2. It carries two Arm Cortex-M33 cores and two open-source Hazard3 RISC-V cores on the same die, and you choose which instruction set runs at boot. One chip, both worlds, and you can benchmark your own firmware on each without changing the board.
That is the real trajectory. Not a war with a winner, but coexistence, where the ISA becomes a design-time option rather than a religion. It also sharpens the choice, because when both cores sit on the same silicon you can measure the trade-off instead of arguing about it. For the underlying part-level detail, the RISC-V microcontrollers explainer goes deeper on the cores themselves.
So which do you pick
If you need the shortest path to a shipping product, the widest silicon choice and a certified stack you can lean on, Arm Cortex-M is still the sane default and will be for a while. If your product lives or dies on unit cost at volume, if royalties are eating your margin, if you need to add custom instructions, or if supply and sovereignty concerns push you off licensed IP, RISC-V has earned a serious look and the ecosystem is closing the gap every quarter.
The reassuring part, and the reason this is a lower-stakes decision than it used to be, is that the abstraction layers have caught up. Write against an RTOS and a HAL and the ISA under your firmware stops being a life sentence. For where all of this is heading across the wider edge, the RISC-V and IoT cornerstone sets out the full picture.
Last updated 23 August 2026. Sources: MCU market share by core architecture (Arm Cortex-M around 68% in 2025, RISC-V roughly 15% CAGR to 2031) per Mordor Intelligence microcontroller market report, January 2026; RP2350 dual-ISA specification (2x Arm Cortex-M33 plus 2x Hazard3 RISC-V, RV32IMAC, ISA selectable at boot) per Raspberry Pi and RISC-V International, 2024; RISC-V toolchain support (GCC, LLVM, OpenOCD) per RISC-V International.
