Machine learning small enough to run on a coin cell
RISC-V and TinyML is edge AI taken to its logical extreme. Forget the gateway with its NPU: this is machine learning running on a microcontroller with kilobytes of memory and a battery meant to last years. It sounds implausible until you see what a tiny model actually needs, and why an open, extensible instruction set is such a good match for it.
The smallest possible AI
The edge AI post was about application-class chips with dedicated accelerators, the sort of thing you find in a smart camera or a gateway. TinyML lives several rungs below that, down where the sensors are. It means running a machine learning model directly on a microcontroller, a device with a few kilobytes of RAM, sometimes running off a coin cell, doing one small useful job.
That job is usually a classification. Is that sound a wake word or just noise. Is that vibration pattern a healthy motor or a failing bearing. Is that motion a gesture or an accident. The model is tiny, the answer is tiny, and that is exactly the point.
Why it matters more than it should
The instinct with a sensor is to send its raw data somewhere cleverer to be understood. The trouble is that raw data is expensive to move. Streaming continuous audio or vibration up a radio link drains the battery in days and racks up a bandwidth bill for the privilege. A device that has to phone home to think is a device tethered to power and network.
TinyML breaks the tether. The sensor senses, a tiny model on the same chip works out what the data means, and only the conclusion travels: a single event, a label, a number. Raw data in, a one-word answer out. That shift is what lets a battery-powered sensor run for years instead of days, and it is why TinyML is one of the most practical ideas in the whole edge story.
Why RISC-V is a natural fit
Any microcontroller can run a small model given the right runtime, and RISC-V parts do. But RISC-V brings one thing to TinyML that a fixed architecture structurally cannot: you can extend the core with your own instructions. If your model spends all its time in one particular operation, you can add a custom instruction, or a small custom function unit, that does exactly that operation in hardware, and get a large speed-up inside a tiny power budget.
This is not theoretical. Efinix’s TinyML platform takes standard TensorFlow Lite Micro models and accelerates them using the custom-instruction capability of its Sapphire RISC-V core, keeping the footprint and power low while dramatically improving performance. A steady stream of research does the same trick with custom function units. On a fixed core you take the maths the vendor gave you. On RISC-V you build the maths your model needs.
This is the RISC-V-specific edge in one line: a tiny model’s hot loop is often a single repeated operation, and on an open ISA you can turn that operation into a bespoke instruction on the core itself. That is how a milliwatt-class RISC-V chip punches above its weight, and it is simply not an option on a locked-down architecture.
The toolchain has grown up
The software side is no longer the obstacle it once was. TensorFlow Lite for Microcontrollers is the de-facto standard runtime, its kernels are optimised for RISC-V among other targets, and a quantised 8-bit model fits in tens of kilobytes of flash. Google’s newer LiteRT for Microcontrollers pushes that further, squeezing basic models into as little as 16 KB. Edge Impulse wraps the whole data-collection, training and deployment loop into one pipeline and supports RISC-V targets. The one genuine irritation is naming: the TFLM-to-LiteRT rebrand has left the ecosystem talking about the same thing under two labels since 2024.
Whichever runtime you pick, the craft is the same. Quantise the model, prune what you can, and tune the memory and timing by hand. TinyML is still an engineering discipline, not a drag-and-drop, but the pathways from prototype to production are now well worn.
Silicon that runs it
| Chip / platform | What it is | Sweet spot |
|---|---|---|
| GreenWaves GAP9 | RISC-V SoC, host core plus 9-core cluster and NE16 accelerator | Audio, hearables, sensor fusion |
| ESP32-C series | RISC-V Wi-Fi and BLE parts running TFLM | Connected sensors with light inference |
| Efinix Sapphire + TinyML | RISC-V soft core with custom-instruction ML acceleration on FPGA | Tunable accelerators, prototyping |
| CH32V003 class | Ultra-cheap RISC-V MCU running low-bit nets | Extreme cost and power constraints |
The ESP32-C parts are the easy on-ramp, since they are cheap, everywhere, and already familiar to anyone who has read the ESP32 and RISC-V piece. The GAP9 is where it gets serious, purpose-built for always-on audio and multi-sensor work.
Where it earns its keep
The killer application is anomaly detection, and the clearest case is predictive maintenance. Bolt a TinyML sensor to a motor, train it on the sound and vibration of a healthy machine, and it will flag the moment things drift toward a failing bearing, sending nothing at all until there is something worth saying. That is a tiny cheap sensor doing work that used to need a technician with a clipboard, and it is exactly the pattern explored in RISC-V in industrial IoT.
Wake-word detection, gesture recognition, presence sensing, environmental classification: they all follow the same shape. Sense locally, decide locally, speak only when it counts. It is the most literal expression of the shift from connected devices to intelligent ones, which is the argument the RISC-V and IoT cornerstone is built around.
Last updated 23 August 2026. Sources: TensorFlow Lite for Microcontrollers targets RISC-V among other architectures with quantised inference in tens of kilobytes per Google and the TFLM project; LiteRT for Microcontrollers fits basic models in as little as 16 KB per Google; GreenWaves GAP9 (RISC-V host core plus nine-core compute cluster and NE16 accelerator) per GreenWaves Technologies; Efinix TinyML platform accelerates TensorFlow Lite Micro via the Sapphire RISC-V core’s custom instructions per Efinix.
