The intelligence moves to where the data is
RISC-V and edge AI is where the whole series thesis comes to a head. The shift from connected devices to intelligent ones means doing the thinking on the device instead of shipping everything to the cloud, and the open, mix-and-match nature of RISC-V turns out to be unusually well suited to building the silicon that does it.
Why the AI is moving to the edge at all
For a decade the pattern was simple: the device sensed, the cloud thought. Cheap sensors squirted raw data up a pipe, a datacentre did the clever part, and an answer came back. It worked, until the cracks showed. Round trips add latency you cannot afford when a machine has to react now. Streaming everything eats bandwidth and the mobile bill that comes with it. Sending raw audio, video and location to someone else’s computer is a privacy problem waiting to happen. And a device that stops working the moment the network drops is a fragile thing to build a business on.
Edge AI is the correction. Do the inference on the device, and you get answers in milliseconds, you send only results instead of raw feeds, the sensitive data never leaves, and the thing keeps working when the link does not. The catch has always been silicon: running real machine learning inside a tight power and thermal budget is hard. That is the problem RISC-V has walked into at exactly the right moment.
The bottleneck nobody mentions
Here is the dirty secret of a lot of edge AI hardware. The compute is not usually the problem. Moving the data is. In a typical design, you have a general CPU, maybe a GPU, and a separate proprietary neural accelerator, each its own island, and you spend a shocking fraction of your power budget just shuttling data between them. At the edge, where every milliwatt counts, that shuttling is the enemy.
This is where the open ISA earns its place. Because RISC-V lets you build the whole thing as one coherent chip, you can put scalar cores, a vector unit and a neural accelerator on a single shared memory fabric. The data stops commuting between separate parts. One tightly integrated system-on-chip handles the control loop, the signal processing and the inference together, and the latency and power both fall.
The real win is integration, not a faster accelerator. Putting the scalar core, the vector unit and the NPU on one open fabric is what stops data shuttling between chips, and that is where the power and latency savings at the edge actually come from. RISC-V makes that kind of custom, unified silicon possible without a licence or a vendor’s permission.
Three ways RISC-V does the maths
The vector extension is the quiet star here. RVV 1.0 brings SIMD-style parallelism into the CPU itself, so an ordinary RISC-V core can accelerate inference and signal processing without a separate accelerator at all. Crucially, since RVA23 made the vector extension mandatory in its baseline profile, every compliant application chip is guaranteed to have it. The extension is important enough to earn its own treatment in the RISC-V vector extension post.
From there, designs scale up in roughly three ways: a discrete NPU sitting next to a RISC-V control core, vector-extended clusters handling inference alongside an NPU for heavier work, and increasingly a unified AI-native design where the acceleration is woven into the architecture itself. Different points on one continuum, all on the same open ISA.
This is real silicon, now
| Silicon / IP | What it is | Edge-AI role |
|---|---|---|
| Google Coral NPU | Open-source RISC-V-based NPU, around 512 GOPS at milliwatts | Always-on AI in wearables and sensors |
| SiFive Intelligence X390 | Vector core with RVV 1.0 and custom AI extensions | Configurable AI accelerator IP |
| MIPS S8200 | RISC-V NPU for autonomous-edge “physical AI” | Real-time inference in robotics and transport |
| StarFive JH8100 | Application SoC with integrated NPU | Edge-AI gateway workloads |
| T-Head TH1520 | Quad-core application SoC with 4 TOPS NPU | Vision and inference on Linux boards |
| SpacemiT K1 | RV64 SoC with RVV 1.0 vector | On-device AI on low-cost boards |
The open-source end of that list matters more than it looks. When the NPU itself is open, the whole pipeline from instruction set to inference can be inspected and audited, which is a genuinely new proposition in AI hardware.
From inference to a working system
Silicon that can think is only useful if the rest of the system knows what to do with the thoughts. On an edge-AI device the pattern is to run the model locally, act on the result on the spot, and pass only the distilled output, an event, a count, an alert, up to a platform. An IoT platform such as ThingsBoard handles that upper layer, collecting the metadata, managing the fleet and running the dashboards, while the raw sensing and inference stay down on the device where they belong.
That “send only what matters” discipline is the whole game at the smallest scale, and it is exactly where the next post picks up, in RISC-V and TinyML. For how edge intelligence fits the larger arc from sensor to gateway to cloud, the RISC-V and IoT cornerstone holds the thread.
Last updated 23 August 2026. Sources: RISC-V heterogeneous SoC integration and RVV 1.0 scalable vector processing per RISC-V International and industry analysis, 2026; Google Coral NPU (open-source, RISC-V-based, around 512 GOPS at a few milliwatts) in the Synaptics Astra SL2610 per Google and Synaptics, October 2025; SiFive Intelligence X390 with RVV 1.0 and custom AI extensions; RVA23 makes the vector extension mandatory per RISC-V International, October 2024. TOPS and GOPS figures are vendor specifications.
