The instruction that does a hundred sums at once
The RISC-V vector extension has turned up in nearly every recent post in this series, doing the heavy lifting behind edge AI and TinyML, so it has earned an explanation of its own. RVV is what lets a RISC-V core chew through big arrays of data at speed, and its one clever trick makes it more portable than any SIMD that came before it.
Scalar versus vector, in plain terms
A normal, scalar instruction does one thing to one number. Add these two values. Multiply that pair. If you want to add up two lists of a thousand numbers each, a scalar processor loops a thousand times, one addition per go. Fine for general code, hopeless for the sort of work modern devices actually spend their time on.
Because the interesting workloads, machine learning, signal processing, image work, audio, cryptography, are all fundamentally the same operation repeated across a big block of data. A vector instruction does exactly that in one shot: apply this operation to this whole array. Where the scalar core takes a thousand instructions, a vector core takes a handful. That is the entire reason vectors exist, and why they used to live only in supercomputers.
The RISC-V twist that changes everything
Vector processing is not new. Intel has AVX, Arm has NEON, and both have been accelerating this kind of maths for years. But they share a limitation baked into their design: the vector width is fixed. NEON works on 128 bits at a time, AVX on 256 or 512. Your code, and your compiled binary, has that width wired into it. Move to hardware with wider vectors and you have to rewrite or recompile to use them.
RVV throws that assumption out. It is vector-length-agnostic, which means the code does not know or care how wide the hardware’s vectors are. You write a loop that says “process the next chunk, whatever size the chip can manage,” and at runtime the hardware tells it. The same binary runs on a tiny embedded core with narrow vectors and a big server core with enormous ones, automatically using every lane available. Arm’s newer SVE does something similar, but for RISC-V it is built in from the start.
Here is why that matters: with NEON or AVX, new vector hardware means a rewrite. With RVV, you write the kernel once and it runs unchanged on a coin-cell sensor’s narrow vector unit and a gateway’s wide one, using whatever lanes each chip has. One binary, the whole range. That is the portability argument of this entire series, now pushed right down to the instruction level.
Where RVV sits in the SIMD landscape
| Extension | Vendor | Width | Length-agnostic | Since |
|---|---|---|---|---|
| SSE | x86 (Intel) | 128-bit fixed | No | 1999 |
| AVX / AVX-512 | x86 (Intel) | 256 / 512-bit fixed | No | 2011 |
| NEON | Arm | 128-bit fixed | No | 2009 |
| SVE | Arm | Scalable, 128 to 2048-bit | Yes | 2016 |
| RVV 1.0 | RISC-V | Scalable | Yes | 2021 |
The interesting company RVV keeps is Arm’s SVE, not the older fixed-width designs. Both bet on scalability, but only one of them is an open standard anyone can implement without a licence.
What it does for connected hardware
For IoT and the edge, the vector extension is the engine under a lot of what the last few posts described. It is what lets an ordinary RISC-V core accelerate the inference in edge AI without bolting on a separate accelerator, and its embedded variants bring a slice of that capability down to the smaller parts. Because RVA23 makes the vector extension mandatory, any application-class chip carrying that badge is guaranteed to have it, which is what lets software vendors rely on it.
The other big beneficiary is anything involving pixels. Image and video work is vector maths through and through, which is why the vector extension is central to the next post, on RISC-V for smart cameras and computer vision. For how all these capabilities ladder up into the intelligent edge, the RISC-V and IoT cornerstone ties it together.
Last updated 23 August 2026. Sources: RVV Version 1.0 ratified by RISC-V International in 2021 (draft v0.7.1, 2019); RVV is a vector-length-agnostic SIMD instruction set with runtime-configurable element size and vector length, unlike the fixed-width x86 AVX and Arm NEON, per RISC-V International and the RVV 1.0 specification; the vector extension is mandatory in the RVA23 profile per RISC-V International, October 2024.
